about makefile using implicit rules

[lswhbcb]

about makefile using implicit rules

I study to write makefile recently.

I wanna write a makefile.rules file for "Make" to separate .obj files from source file ("./src").but I meet some trouble to come true my ideal.

The file is like below:

##================================================ ========================##
ALL_FILES = ./src/example.c ./src/methods/gauss.c ./src/methods/iterate.c
OBJDIR = ./obj
OBJ=./obj/example.o ./obj/gauss.o ./obj/iterate.o

OUTFILE := ./prg
CC := gcc
DEBUG_CFLAGS := -g
DEBUG_LINK_CFLAGS := -g -o

OUTFILE := prg

COMPILE =$(CC) $(DEBUG_CFLAGS) -c $< -o $@
PRG_LINK=$(CC) $(DEBUG_LINK_CFLAGS) "$(OUTFILE)" $(OBJ)


define targe_template
$(1):$(filter $(patsubst %.o,%.c,$(notdir $(1))), $(ALL_FILES))
$(COMPILE) ##TAB before the command
endef

$(foreach obj, $(OBJ),$(eval $(call targe_template ,$(obj)))))

all:$(OBJ)
##================================================ ========================#

Makefile:18: *** missing separator. Stop.(why? )

I know there is a style "%.o : %.c" , so i try to use "$(OBJDIR)/%.o:%.c" first but fail (i think that "make" would find the source file path automaticlly).

so I use "$($(OBJDIR)/%.o:$( filter $* , $(ALL_FILES)) $(warning $*) " instead, but the output of "$*" is NULL. I do know why. Finally, I change the file as above, to run it is also fail.

I have not ideas , please help me, thx!